1. Field of the Invention
The present invention relates to a technique of extracting a clock signal from input data in an LSI at the receiving end in the serial transmission of data between LSIs.
2. Description of Related Art
With the progress of semiconductor technology, data transmission between LSIs is serialized. In order to reduce electromagnetic interface (EMI) in the serial data transmission, there is known a technique of performing frequency modulation using a spread spectrum clock in an LSI at the transmitting end and then extracting a clock from frequency-modulated serial data by a clock and data recovery circuit in an LSI at the receiving end.
FIG. 7 is the illustration shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2005-5999, and it shows the clock and data recovery circuit which is disclosed therein. The clock and data recovery circuit includes a phase detector 101, an integrator 102, an integrator 103, a pattern generator 104, a mixer 105, and a phase interpolator 106. The phase detector 101 compares the phase of input serial data with the phase of a synchronous clock signal which is output from the phase interpolator 106 and outputs a comparison result. Based on the comparison result, a frequency tracking loop which is formed by the integrator 103 and the pattern generator 104 tracks the phase shift at low frequencies or the frequency shift, and a phase tracking loop which is formed by the integrator 102 tracks the phase shift at high frequencies which cannot be tracked by the frequency tracking loop. The mixer 105 mixes the results of the frequency tracking loop and the phase tracking loop. Based on the mixture result, the phase of the synchronous clock signal which is output from the phase interpolator 106 is controlled, thereby extracting the clock of the serial data.
The phase detector 101 detects a difference in phase between the serial data and the synchronous clock signal and outputs an up signal UP1 or a down signal DOWN1 which indicates the difference as a comparison result. The integrator 102 and the integrator 103 are up/down counters that smooth the comparison result to obtain UP2/DOWN2 and UP3/DOWN3, respectively, and output them as control signals. The integrator 102 and the integrator 103 respectively have a predetermined count width. The pattern generator 104 generates a control signal UP4/DOWN4 for correcting the frequency of the synchronous clock signal based on the control signal UP3/DOWN3.
The phase detector 101 outputs “1” for the up signal UP1 when the phase of the synchronous clock signal should be advanced. On the other hand, the phase detector 101 outputs “1” for the down signal DOWN1 when the phase of the synchronous clock signal should be delayed.
Because the phase tracking loop tracks the high-frequency phase shift and the frequency tracking loop tracks the frequency shift or the low-frequency phase shift, the count width of the integrator 102 is set to be smaller than the count width of the integrator 103. The integrator 102 and the integrator 103 operate in the same manner except that the count width is different, and thus the integrator 103 only is described hereinafter.
The integrator 103 counts from “−m” to “+m” and the count width is “m+1” (m is an integer). The integrator 103 counts up when UP1 is “1” and counts down then DOWN1 is “1”. When the count value is “+m” and UP1 is “1”, the integrator 103 outputs “1” for UP3 and performs clear operation which sets the count value back to 0. When the count value is “−m” and DOWN1 is “1”, the integrator 103 outputs “1” for DOWN3 and performs clear operation which sets the count value back to 0.
In this manner, the signals UP1 and DOWN1 are smoothed by the integrator 103. As the count width of the integrator 103 is larger, the period of smoothing UP1 and DOWN1 is longer. Thus, the count width of the integrator 103 is a smoothing period.
The signal UP3/DOWN3 which is output from the integrator 103 is input to the pattern generator 104.
FIG. 8 is the illustration shown in FIG. 7 of Japanese Unexamined Patent Application Publication No. 2005-5999, and it shows the configuration of the pattern generator 104. The pattern generator 104 includes a counter 141 that receives a clock signal and repeatedly counts from 0 to a predetermined upper limit in synchronization with the clock, an up/down counter 142 that receives the control signal UP3/DOWN3 from the integrator 103 and the clock signal and counts up or counts down, and a decoder 143 that receives and decodes the count values from the counter 141 and the up/down counter 142 and outputs it as a result of the frequency tracking loop.
The pattern generator 104 outputs “1” for UP4 which indicates that the phase of the clock signal is advanced or outputs “1” for DOWN4 which indicates that the phase of the clock signal is delayed, respectively several times in each period with a predetermined length that is represented by the number of clocks or cycles. The frequency of outputting “1” for UP4 or outputting “1” for DOWN4 in each period is determined by the state of UP3/DOWN3 from the integrator 103. Specifically, if UP3 with “1” is output successively, the frequency of outputting “1” for UP4 increases or the frequency of outputting “1” for DOWN4 decreases. On the other hand, if DOWN3 with “1” is output successively, the frequency of outputting “1” for DOWN4 increases or the frequency of outputting “1” for UP4 decreases.
The length which is represented by the number of cycles is called a pattern length of the pattern generator 104. The pattern length of the pattern generator 104 is determined by the count width of the counter 141. The count width of the up/down counter 142 is generally the same as the count width of the counter 141. For example, if the counter 141 counts from “0” to “k” (k is an integer) and the count width is “k+1”, the up/down counter 142 generally counts from “−k” to “+k” and the count width at one side is “k+1”. The pattern length of the pattern generator 104 is “k+1”. The count width of the up/down counter 142 may be different from the count width of the counter 141.
FIG. 9 is the illustration shown in FIG. 10 of Japanese Unexamined Patent Application Publication No. 2005-5999, and it shows another clock and data recovery circuit which is disclosed therein. The clock and data recovery circuit is different from the clock and data recovery circuit shown in FIG. 7 in that the frequency tracking loop and the phase tracking loop share the integrator 102.
As described in the foregoing, in the frequency tracking loop of the clock and data recovery circuit shown in FIG. 7, as the count width of the integrator 103 is larger, the smoothing period is longer, so that the frequency tracking loop is less sensitive to the phase shift of serial data. This deteriorates the effect of frequency correction of the clock and data recovery circuit and thereby decreases the tolerance to jitter at low frequencies (which is referred to simply as jitter tolerance).
On the other hand, as the count width of the integrator 103 is smaller, the smoothing period is shorter, so that the frequency tracking loop is more sensitive to the phase shift of serial data. The inventor of the present invention has studied and found that overcorrection of a frequency occurs in a particular frequency range to cause a decrease in jitter tolerance. This is possibly because if the count width of the integrator 103 is small, the phase is fed back with a delay with respect to input jitter in the frequency tracking loop.
This is the same for the clock and data recovery circuit shown in FIG. 9.